Optimized photodiode process for improved transfer gate leakage

ABSTRACT

An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.

FIELD OF THE INVENTION

The present invention relates to improved photodiodes used in pixels ofan image array.

BACKGROUND OF THE INVENTION

CMOS image devices having pixel sensor arrays are well known in the artand have been widely used due to their low voltage operation and lowpower consumption. CMOS image devices further have advantages of beingcompatible with integrated on-chip electronics, allowing random accessto the image data, and having lower fabrication costs as compared toother imaging technologies. CMOS image devices are generally disclosedfor example, in Nixon et al., “256×256 CMOS Active Pixel SensorCamera-on-a-Chip,” IEEE Journal of Solid State Circuits, vol. 31(12) pp.2046-2050, 1996; Mendis et al., CMOS Active Pixel Image Sensors,” IEEETransactions on Electron Devices, vol. 41(3) pp. 452-453, 1994 as wellas U.S. Pat. Nos. 5,708,263, 5,471,515, and 6,291,280, which are herebyincorporated by reference.

However, conventional CMOS image devices have some significantdrawbacks. When photodiode implants are formed within a semiconductorsubstrate of a pixel cell adjacent a transfer transistor to transfercharge from the photodiode, the resulting structure creates leakageproblems beneath the transfer gate, particularly during chargeintegration, when the transfer transistor is off. FIG. 1 illustrates aprior art pixel cell 750 with a n-type photodiode implant 705 set in ap-type substrate 915, wherein the implant is on one side of transfergate 701, with a floating diffusion region 702 on the opposite side ofgate 701. STI region 707 is an isolation region which isolates one pixelfrom another. The n-type photodiode implant 705 forms a P—N diodejunction above implant 705 with the p-type material which is overimplant 705.

The photodiode implant 705 is typically formed using an implant angleθ(706) in order to extend the implant slightly under gate 701 to providesufficient conductivity between the photodiode n-region 705 and thechannel region beneath transfer gate 701. Once implanted, the resultingextended photodiode n-region 705 facilitates transfer of electrons tothe channel beneath gate 701 and to the floating diffusion 702 when thegate 701 is on (e.g., a positive voltage applied which is greater thanthe threshold of the transfer transistor formed by gate 701 and implantregions 702, 705). However, as is shown in FIG. 2, when transfer gate701 is off, residual charge from n-region 705 leaks in the direction ofarrows 800 beneath transfer gate 701 to floating diffusion region 702.This is due to the fact that the shallow angled implant results in ashape for n-region 705, where a portion of the photodiode is in veryclose proximity to the transfer gate 701. This proximity, whileproviding a good charge transfer when gate 701 is on, has the unwantedby-product of some undesirable charge leakage when the gate 701 is off.Accordingly, a better photodiode implant which provides good chargetransfer when gate 701 is on, while lowering leakage when gate 701 isoff is needed.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a CMOS imager having a pixel array inwhich each pixel has an improved photodiode implant. The photodiodeimplant is created by tailoring the angle of a plurality of chargecollection region implants so that the resulting charge collectionregion is positioned to provide a good charge transfer characteristicwhen the transfer transistor gate is on and lowered leakage across thechannel region when the transistor gate is off. The photodiode chargecollection region is formed through the successive implants into thesubstrate, some of which are angled, to minimize the barrier and in turnminimize the leakage.

The above and other advantages and features of the invention will bemore clearly understood from the following detailed description which isprovided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a partially cut away side view of a prior art angled diodeimplant in a semiconductor imager;

FIG. 2 illustrates the leakage occurring beneath transfer gate 701 inthe FIG. 1 arrangement;

FIG. 3A shows a first reduced-angle diode implant in accordance with afirst embodiment of the invention;

FIG. 3B shows a second reduced-angle diode implant in accordance withthe first embodiment of the invention;

FIG. 3C shows a third reduced-angle diode implant in accordance with thefirst embodiment of the invention;

FIG. 3D shows a supplemental implant to the reduced-angle diode implantin accordance with a second embodiment of the invention;

FIG. 4 illustrates an electrostatic potential contour of thediode/transfer gate region formed in a substrate and the donorconcentrations in accordance with a third embodiment of the invention;

FIG. 5 illustrates an electrostatic potential contour of thediode/transfer gate region formed in a substrate and the donorconcentrations in accordance with a fourth embodiment of the invention;

FIG. 6 illustrates an electrostatic potential contour of thediode/transfer gate region formed in a substrate and the donorconcentrations in accordance with a fifth embodiment of the invention;

FIG. 7 illustrates an electrostatic potential contour of thediode/transfer gate region formed in a substrate and the donorconcentrations in accordance with a sixth embodiment of the invention;

FIG. 8 illustrates an electrostatic potential contour of thediode/transfer gate region formed in a substrate and the donorconcentrations in accordance with a seventh embodiment of the invention;and

FIG. 9 is an illustration of a computer system having a CMOS imageraccording to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

The terms “wafer” and “substrate” are to be understood as includingsilicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. In addition, the semiconductor need not besilicon-based, but could be based on silicon-germanium, germanium, orgallium arsenide. Furthermore, when reference is made to a “wafer” or“substrate” in the following description, previous process steps mayhave been utilized to form regions or junctions in the basesemiconductor structure or foundation.

The term “pixel” refers to a picture element unit cell containing aphotosensor and transistors for converting electromagnetic radiation toan electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein, andtypically fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

Fabrication of a photodiode adjacent a transfer gate in accordance witha first embodiment of the invention will now be described. Referring toFIG. 3A, a portion of a substrate having a p-type doping region 915 isillustrated, where a photodiode will be produced. It is understood thatthe CMOS imager of the present invention can also be fabricated usingn-doped regions in an p-well. A transfer gate stack 940 is fabricatedover the substrate region 915. Any LDD source/drain implant associatedwith region 702 and with other transistors being fabricated on the samestructure are performed and a photolithography resist 950 is thenapplied, having an opening 949 through which a doping implant for aphotodiode can pass. The gate stack 940 contains a gate oxide and aconductor, where an insulator is placed over the conductor. Theconductor may be formed from material such as poly-silicon, silicide,metal, or a combination. The insulator may be formed from material suchas oxide, nitride, metal oxide, or a combination.

FIG. 3A illustrates a first n-type diode implant (PD1) 900, formed inp-type substrate 915 through resist opening 949 at a depth indicated as903, wherein the depth 903 is in the range of 0.1 to 0.7 microns,preferably 0.1-0.5. The dopants for the implant 900 are implanted at anangle θ1, shown as arrow 910, towards the transfer gate 940. Angle θ₁ ismeasured away from a line normal to the surface of the sensor, as shownin FIG. 3A. Angle θ₁ for implant 900 is set in the range of 0-30° normalto the surface of sensor 920, preferably at 0-15°. Implant 900 ispreferably a low energy implant, where the implant energy used forimplant 900 is in the range of 5-200 KeV, preferably less than 100 KeV.The implant dose for implant 900 is in the range of 2E11-1E13/cm²,preferably 1E12-6E12/cm².

FIG. 3B illustrates a second n-type diode implant (PD2) 901, placed inp-type substrate 915 at a depth illustrated as 904, wherein implant 901may be set forward from implant 900 in the direction of transfer gate940, by a distance 906 as shown in FIG. 3B. The dopants for the implant901 are set at an angle θ₂ towards the transfer gate. Angle θ₂ ismeasured away from a line normal to the surface of the sensor, as shownin FIG. 3B. Angle θ₂ for implant 901 is preferably set in the range of0-30° normal to the surface of sensor 920, preferably at 0-15°. Implant901 is preferably a higher energy implant than that used for implant900, where the implant energy for implant 901 is in the range of 30-300KeV, preferably 50-250 KeV. The implant dose for implant 901 is in therange of 2E11-1E13/cm², preferably 1E12-6E12/cm².

FIG. 3C illustrates a third n-type diode implant (PD3) 902, placed inp-type substrate 915 at a minimum depth indicated as 905, whereinimplant 902 may be offset from implant 901 by a distance 907 as shown inFIG. 3B. The dopants for the diode are implanted 912 at an angle θ₃towards the transfer gate. Angle θ₃ is measured away from a line normalto the surface of the sensor, as shown in FIG. 3B. Angle θ₃ for implant902 is preferably set in the range of 0-30° normal to the surface ofsensor 920. Implant 902 is preferably a high energy deep implant, wherethe implant energy for implant 902 is in the range of 60-500 KeV,preferably 100-400 KeV. The implant dose for implant 902 is in the rangeof 2E11-1E13/cm², preferably 1E12-6E12/cm². Once formed, the implants(900, 901, 902) of FIG. 3A-C collectively form an n-type electroncollection 930 forming part of a photodiode with a p-type region 947,residing over region 930. Under the illustrations of FIGS. 3A-C, atleast one of the implants must be angled.

FIG. 3D illustrates an alternate embodiment of the present invention,wherein three implants 900, 901 and 902 are implanted into a p-typesubstrate 915. The implants 900, 901 and 902, are placed in substrate915 in a manner similar to that described in the embodiment of FIG.3A-C, except that the implant angle for each of the implants (θ₁, θ₂,and θ₃) is reduced to a range of 0-5°, where at least one of theimplants 901 and 902 has an implant angle greater than 0°. Once theimplants have been set, a fourth light implant (PD 4) 920 is made in theregion of the second 901 implant, on the side closest to the transfergate. The fourth implant is inserted 913 at an increased angle θ₄,wherein the implant angle θ₄ is measured away from a line normal to thesurface of the substrate, as shown in FIG. 3D, and is preferably in therange of 10-30° of normal. Exemplary implant doses for the fourthimplant may be in the range of 2e11/cm²-5e12/cm². It is understood thatthe order of the implants (900, 901, 902 and 904 (if provided)) is notcritical; each of the disclosed implants may be arranged in any order.

FIGS. 4-8 show doping profiles in a partially cut away side view ofangled diode implants for the implanted photodiode region 930, whereinthe various drawings illustrate the dopant concentrations resulting fromdifferent exemplary angled implants that may be used. FIG. 4 shows adiode region 930A that is formed in a substrate 915 as a result of theimplant methods discussed above in FIG. 3A-C. Specifically, FIG. 4illustrates a transfer gate 940, surrounded by an insulating layer 102,formed over a substrate 915, which also has an implant n-type floatingdiffusion region 702. Region 930A represents n-type charge collectionregion of the photodiode formed in accordance with the three-implantprocess described above in connection with FIGS. 3A-3C, wherein theimplant angles of PD1-PD3 are set at θ₁=5′ for PD1 region 900 (see FIG.3A), θ₂=5′ for PD2 region 901 (see FIG. 3B), and θ₃=30° for PD3 region902 (see FIG. 3C). FIG. 4 also shows four concentration regions (I-IV)that are formed in the substrate as a result of the three implants atthe specified implant angles (θ₁=5°, θ₂=5°, and θ₃=30°).

Region I, generally defined by the region above 130 and below regions104 and floating diffusion 702, has the largest donor concentrationbetween the range of just over 5E16/cm³ to 5E17/cm³. Region II,generally defined by the region between 125 and 130, has a lesser donorconcentration between the ranges of just over 5E15/cm³ to 5E16/cm³.Region III, generally defined by the region between 120 and 125, has yeta smaller donor concentration between the ranges of just over 1E14/cm³to 5E15/cm³. Region IV, generally defined by the region below 120,contains the lowest donor concentration at or below 1E14/cm³. As can beseen from FIG. 4, the reduced donor concentrations found in region IInear the transfer gate 940 creates a potential barrier wherein theamount of donor impurities under the transfer gate 940 is reduced. Thisreduction lessens the occurrence of short-channel effects orpunch-through beneath the gate 940.

FIG. 5 illustrates region 930B in accordance with another embodiment ofthe invention. Region 930B in FIG. 5 represents the diode formedsubsequent to the three-implant process described above, wherein theimplant angles of PD1-PD3 are set at θ₁=5′ for PD1 (see FIG. 3A), θ₂=5°for PD2 (see FIG. 3B), and θ₃=15° for PD3 (see FIG. 3C). FIG. 5 alsoshows four concentration regions (I-IV) that are formed in the substrateas a result of the diode region 930B formed by the three implants at thespecified implant angles (θ₁=5°, θ₂=5°, and θ₃=15°).

Region I, generally defined by the region above 131 and below regions104 and floating diffusion 702, has the largest donor concentrationbetween the range of just over 5E16/cm³ to 5E17/cm³. Region II,generally defined by the region between 126 and 131, has a lesser donorconcentration between the ranges of just over 5E15/cm³ to 5E16/cm³.Region III, generally defined by the region between 121 and 126, has yeta smaller donor concentration between the ranges of just over 1E14/cm³to 5E15/cm³. Region UV, generally defined by the region below 121,contains the lowest donor concentration at or below 1E14/cm³. As can beseen in the electrostatic potential contour illustration, the reductionof the implant angle θ₃ from 30° to 15° from the previous embodiment hasresulted in a wider expansion of Region II from the previous embodiment,directly beneath gat 940, resulting in a further reduction in donorimpurities underneath the transfer gate 940.

FIG. 6 illustrates a doping profile in accordance with a third exemplaryembodiment of the invention, where a transfer gate 940 is surrounded bya insulating layer 102, formed over a substrate 915, which also havingan implanted floating diffusion region 702. Region 930C in FIG. 6represents the diode region formed subsequent to the three-implantprocess described above, wherein the implant angles of PD1-PD3 are setat θ₁=5° for PD1 (see FIG. 3A), θ₂=30° for PD2 (see FIG. 3B), and θ₃=5°for PD1 (see FIG. 3C). FIG. 6 also shows four concentration regions(I-IV) that are formed in the substrate as a result of the diode region930C formed by the three implants at the specified implant angles(θ₁=5°, θ₂=30°, and θ₃=5°).

Region I, generally defined by the region above 132 and below regions104 and floating diffusion 702, has the largest donor concentrationbetween the range of just over 5E16/cm³ to 5E17/cm³. Region II,generally defined by the region between 127 and 132, has a lesser donorconcentration between the ranges of just over 5E15/cm³ to 5E16/cm³.Region III, generally defined by the region between 122 and 127, has yeta smaller donor concentration between the ranges of just over 1E14/cm³to 5E15/cm³. Region IV, generally defined by the region below 122,contains the lowest donor concentration at or below 1E14/cm³. As can beseen in the electrostatic potential contour, the reduction of theimplant angles θ₃ from 15° to 5°, and the increase of implant angle θ₂from 5° to 30° from the previous embodiment has resulted in even a widerexpansion of Region II from the previous embodiment, directly beneathgat 940, resulting in a further reduction in donor impurities underneaththe transfer gate 940.

FIG. 7 illustrates a doping profile in accordance with a fourthexemplary embodiment of the invention. Region 930D in FIG. 7 representsthe diode formed subsequent to the three-implant process describedabove, wherein the implant angles of PD1-PD3 are set at θ₁=5′ for PD1(see FIG. 3A), θ₂=15° for PD2 (see FIG. 3B), and θ₃=5° for PD1 (see FIG.3C). FIG. 7 also shows four concentration regions (I-IV) that are formedin the substrate as a result of the diode region 930D formed by thethree implants at the specified implant angles (θ₁=5°, θ₂=15°, andθ₃=5°).

Region I, generally defined by the region above 133 and below regions104 and floating diffusion 702, has the largest donor concentrationbetween the range of just over 5E16/cm³ to 5E17/cm³. Region II,generally defined by the region between 128 and 133, has a lesser donorconcentration between the ranges of just over 5E15/cm³ to 5E16/cm³.Region III, generally defined by the region between 123 and 128, has yeta smaller donor concentration between the ranges of just over 1E14/cm³to 5E15/cm³. Region IV, generally defined by the region below 123,contains the lowest donor concentration at or below 1E14/cm³. Thereduction of the implant angles θ₂ from 30° to 15° from the previousembodiment resulted in slightly wider expansion of Region II from theprevious embodiment, directly beneath gate 940, resulting in a furtherreduction in donor impurities underneath the transfer gate 940.

FIG. 8 illustrates a doping profile concentration in accordance with afifth exemplary embodiment. Region 930E in FIG. 8 represents the dioderegion formed subsequent to the three-implant process described above,wherein the implant angles of PD1-PD3 are set at θ₁=5′ for PD1 (see FIG.3A), θ₂=5 for PD2 (see FIG. 3B), and θ₃=5° for PD1 (see FIG. 3C). FIG. 8also shows four concentration regions (I-IV) that are formed in thesubstrate as a result of the diode region 930E formed by the threeimplants at the specified implant angles (θ₁=5°, θ₂=5°, and θ₃=5°).

Region I, generally defined by the region above 134 and below regions104 and floating diffusion 702, has the largest donor concentrationbetween the range of just over 5E16/cm³ to 5E17/cm³. Region II,generally defined by the region between 129 and 134, has a lesser donorconcentration between the range of just over 5E15/cm³ to 5E16/cm³.Region III, generally defined by the region between 124 and 129, has yeta smaller donor concentration between the range of just over 1E14/cm³ to5E15/cm³. Region IV, generally defined by the region below 124, containsthe lowest donor concentration at or below 1E14/cm³. As can be seen inthe electrostatic potential contour illustration, the reduction of theimplant angles θ₂ from 15° to 5° from the previous embodiment hasfurther expanded Region II from the previous embodiment, resulting in aneven greater reduction in donor impurities underneath the transfer gate940.

A typical processor system which includes a CMOS imager device havingpixels constructed according to the present invention is illustratedgenerally in FIG. 9. A pixel imager array having pixels constructed asdescribed above may be used in an imager device having associatedcircuits for reading images captured by the pixel array. The imagerdevice may, in turn, be coupled to a processor system for further imageprocessing.

As can be seen from the process depicted in FIGS. 3A-3C and 3A-3D and inthe specific examples, a portion of the implanted photo-diode region 930which is deeper into substrate 915 extends as much or less towards thetransfer gate 940, than a portion of the implanted photodiode regionwhich does not extend as deep into the substrate. This reduces any shortchannel effect, as well as any associated transfer gate leakage, ascompared to the photodiode implant depicted in FIG. 2.

A processor system which uses a CMOS imager having pixels fabricated inaccordance with the invention, for example, generally comprises acentral processing unit (CPU) 1544 that communicates with aninput/output (I/O) device 1546 over a bus 1552. The CMOS imager 1510also communicates with the system over bus 1552. The computer system1500 also includes random access memory (RAM) 1548, and, in the case ofa computer system may include peripheral devices such as a floppy diskdrive 1554 and a compact disk (CD) ROM drive 1556 which also communicatewith CPU 1544 over the bus 1552. As described above, CMOS imager 1510 iscombined with a pipelined JPEG compression module in a single integratedcircuit.

It should again be noted that although the invention has been describedwith specific reference to CMOS imaging circuits having a photodiode anda floating diffusion, the invention has broader applicability and may beused in forming a photodiode structure adjacent a transfer gate in anyCMOS imaging apparatus. For example, the CMOS imager array can be formedon a single chip together with the logic or the logic and array may beformed on separate IC chips. In addition to transfer gates, theconfiguration is equally applicable to other gates, such as reset gates,global shutter, storage gate, high dynamic range gate, etc. Moreover,the implantation process described above is but one method of many thatcould be used. The implantation process can further be implemented on avariety of image pixel circuits, including three transistor (3T), fourtransistor (4T) five transistor (5T), six transistor (6T) or seventransistor (7T) structures. Accordingly, the above description andaccompanying drawings are only illustrative of preferred embodimentswhich can achieve the features and advantages of the present invention.It is not intended that the invention be limited to the embodimentsshown and described in detail herein. The invention is only limited bythe scope of the following claims.

1. An image pixel structure, comprising: a semiconductor substrate of afirst conductivity type having a surface; a gate over a surface of thesubstrate; and a photodiode within said substrate, said photodiodeincluding an implant region of a second conductivity type, a portion ofwhich extends further towards a region of said substrate beneath saidgate than another portion of said implant region.
 2. The image pixelstructure of claim 1, wherein the substrate is p-type, and the implantsare n-type.
 3. The image pixel structure of claim 1, wherein thesubstrate is n-type, and the implants are p-type.
 4. The image pixelstructure of claim 1, wherein an upper portion of said implant region isfarther away from the region beneath said gate than the other portionsof the implant.
 5. The image pixel structure of claim 1, wherein theimplant region includes a first portion, said first portion beingnearest the substrate surface in the implant region.
 6. The image pixelstructure of claim 5, wherein the implant dose of the first portion isbetween 2E11-1E13/cm².
 7. The image pixel structure of claim 5, whereinthe implant region includes a second portion, said second portion beingunderneath the first portion in the implant region.
 8. The image pixelstructure of claim 7, wherein the implant dose of the second portion isbetween 2E11-1E13/cm².
 9. The image pixel structure of claim 7, whereinthe implant region includes a third portion, said third portion beingunderneath the second portion in the implant region.
 10. The image pixelstructure of claim 9, where the implant dose of the third portion isbetween 2E11-1E13/cm².
 11. The image pixel structure of claim 9, whereinthe first, second, and third portions of the implant region are formedby implants angled between 0 and 30 degrees in the direction of thegate, said angle being measured away from a line normal to the surfaceof the substrate, with at least one of the implants being at an anglegreater than 0 degrees.
 12. The image pixel structure of claim 11,wherein the third portion extends further than the first and secondportions towards the region of said substrate beneath said gate.
 13. Theimage pixel structure of claim 9, wherein the implant angle for thefirst and second portions of the implant region is between 0-15 degrees,and the implant angle for the third portion is between 0-30 degrees, atleast one of said implant angles being greater than 0 degrees.
 14. Theimage pixel structure of claim 12, wherein the implant angle for thefirst and second portions of the implant region is between 0-10 degrees,and the implant angle for the third portion is between 0-15 degrees. 15.The image pixel structure of claim 11, wherein the second portionextends further than the first and third portions towards the region ofsaid substrate beneath said gate.
 16. The image pixel structure of claim9, wherein the implant region includes a fourth portion, said fourthportion being lateral to the second portion in the direction of thegate.
 17. The image pixel structure of claim 16, where the implant doseof the fourth portion is between 2E11-1E13/cm².
 18. The image pixelstructure of claim 16, wherein the fourth portion extends further thanthe first, second, and third portions towards the region of saidsubstrate beneath said gate.
 19. The image pixel structure of claim 18,wherein the first, second, and third portions of the implant region areformed by implants angled between 0 and 5 degrees in the direction ofthe gate, said angle being measured away from a line normal to thesurface of the substrate.
 20. The image pixel structure of claim 19,wherein the fourth portion is formed by an implant angled between 10 and30 degrees in the direction of the gate, said angle being measured awayfrom a line normal to the surface of the substrate.
 21. The image pixelstructure of claim 1, wherein at least one of said portions of saidimplant region is angled.
 22. The image pixel structure of claim 1,wherein the image pixel structure is a CCD imager.
 23. The image pixelstructure of claim 1, wherein the image pixel structure is a CMOSimager.
 24. The image pixel structure of claim 23, wherein said imagepixel structure is one of a three transistor (3T), four transistor (4T)five transistor (5T), six transistor (6T) and seven transistor (7T)structure.
 25. The image pixel structure of claim 1, wherein said gateincludes a gate oxide and a conductor.
 26. The image pixel structure ofclaim 25, wherein said conductor contains at least one of poly-silicon,silicide, metal, and any combination of poly-silicon, silicide andmetal.
 27. The image pixel structure of claim 25, wherein said gateincludes an insulator over the conductor.
 28. The image pixel structureof claim 27, wherein the insulator is formed from at least one of oxide,nitride, metal oxide, and any combination of oxide, nitride, and metaloxide.
 29. A method of forming a region in an image sensor comprising:forming a semiconductor substrate of a first conductivity type having asurface; forming a gate on the surface of the substrate; and forming animplant region within said substrate of a second conductivity type,wherein a portion of said implant region extends further towards aregion of said substrate beneath said gate, than another portion of saidimplant region.
 30. The method according to claim 29, wherein thesubstrate is formed with p-type material, and the implants are formed byn-type materials.
 31. The method according to claim 29, wherein thesubstrate is formed with n-type material, and the implants are formed byp-type materials.
 32. The method according to claim 29, wherein an upperportion of said implant region is farther away from the region beneathsaid gate than the other portions of the implant.
 33. The method ofclaim 29, wherein the forming of the implant region includes forming afirst portion, said first portion being nearest the substrate surface inthe implant region.
 34. The method of claim 33, wherein the firstportion is formed from an implant energy ranging between 5-200 KeV. 35.The method of claim 33, wherein the forming of the implant regionincludes forming a second portion, said second portion being underneaththe first portion in the implant region.
 36. The method of claim 35,wherein the second portion is formed from an implant energy rangingbetween 30-200 KeV.
 37. The method of claim 35, wherein the forming ofthe implant region includes forming a third portion, said third portionbeing underneath the second portion in the implant region.
 38. Themethod of claim 37, wherein the third portion is formed from an implantenergy ranging between 60-300 KeV.
 39. The method of claim 37, whereinat least one of said first, second, and third portions of the implantregion is formed by implants angled between 0 and 30 degrees in thedirection of the gate, said angle being measured away from a line normalto the surface of the substrate, at least one of said portions having animplant angle greater than 0 degrees.
 40. The method of claim 39,wherein the third portion extends further than the first and secondportions towards the region of said substrate beneath said gate.
 41. Themethod of claim 40, wherein the implant angle for the first and secondportions of the implant region is 0-15 degrees, and the implant anglefor the third portion is 0-30 degrees, wherein at least one of the firstand second portions is angled greater than 0 degrees.
 42. The method ofclaim 39, wherein the second portion extends further than the first andthird portions towards the region of said substrate beneath said gate.43. The method of claim 42, wherein the implant angles for the first,second and third portions of the implant region are 0-15 degrees, 0-30degrees, and 0-30 degrees, respectively, wherein at least one of theimplants is angled greater than 0 degrees.
 44. The method of claim 37,wherein the forming of the implant region includes a fourth portion,said fourth portion being lateral to the second portion in the directionof the gate.
 45. The method of claim 44, wherein the fourth portion isformed from an implant energy ranging between 50-150 KeV.
 46. The methodof claim 44, wherein the fourth portion extends further than the first,second, and third portions towards the region of said substrate beneathsaid gate.
 47. The method of claim 44, wherein at least one of saidfirst, second, and third portions of the implant region are formed byimplants angled between 0 and 10 degrees in the direction of the gate,said angle being measured away from a line normal to the surface of thesubstrate.
 48. The method of claim 47, wherein the implant angle of thefourth portion is between 10 and 30 degrees.
 49. The method of claim 35,wherein at least one of said first and second portions of implant regionare formed by implants angled between 0-30 degrees in the direction ofthe gate, said angle being measured away from a line normal to thesurface of the substrate.
 50. The method of claim 29, wherein said gateincludes a gate oxide and a conductor.
 51. The method of claim 50,wherein said conductor contains at least one of poly-silicon, silicide,metal, and any combination of poly-silicon, silicide and metal.
 52. Themethod of claim 29, wherein said gate includes an insulator over theconductor.
 53. The image pixel structure of claim 52, wherein theinsulator is formed from at least one of oxide, nitride, metal oxide,and any combination of oxide, nitride, and metal oxide.
 54. A pixelimager system, comprising: (i) a processor; and (ii) a CMOS imagingdevice coupled to said processor and including: a pixel array, at leastone pixel of said array comprising: a semiconductor substrate of a firstconductivity type having a surface; a gate over a surface of thesubstrate; and a photodiode, within said substrate, said photodiodeincluding an implant region of a second conductivity type, a portion ofsaid implant region which extends further towards a region of saidsubstrate beneath said gate than another portion of said implant region.55. The pixel imager system of claim 54, wherein the substrate isp-type, and the implants are n-type.
 56. The pixel imager system ofclaim 54, wherein the substrate is n-type, and the implants are p-type.57. The pixel imager system of claim 54, wherein an upper portion ofsaid implant region is farther away from the region beneath said gatethan the other portions of the implant.
 58. The pixel imager system ofclaim 54, wherein the implant region includes a first portion, saidfirst portion being nearest the substrate surface in the implant region.59. The pixel imager system of claim 58, wherein the implant dose of thefirst portion is between 2E11-1E13/cm².
 60. The pixel imager system ofclaim 58, wherein the implant region includes a second portion, saidsecond portion being underneath the first portion in the implant region.61. The pixel imager system of claim 60, wherein the implant dose of thesecond portion is between 2E11-1E13/cm².
 62. The pixel imager system ofclaim 60, wherein the implant region includes a third portion, saidthird portion being underneath the second portion in the implant region.63. The pixel imager system of claim 62, where the implant dose of thethird portion is between 2E11-1E13/cm².
 64. The pixel imager system ofclaim 62, wherein the first, second, and third portions of the implantregion are formed by implants angled between 0 and 30 degrees in thedirection of the gate, said angle being measured away from a line normalto the surface of the substrate, with at least one of the implants beingat an angle greater than 0 degrees.
 65. The pixel imager system of claim64, wherein the third portion extends further than the first and secondportions towards the region of said substrate beneath said gate.
 66. Thepixel imager system of claim 62, wherein the implant angle for the firstand second portions of the implant region is between 0-15 degrees, andthe implant angle for the third portion is between 0-30 degrees, atleast one of said implant angles being greater than 0 degrees.
 67. Thepixel imager system of claim 65, wherein the implant angle for the firstand second portions of the implant region is between 0-10 degrees, andthe implant angle for the third portion is between 0-15 degrees.
 68. Thepixel imager system of claim 64, wherein the second portion extendsfurther than the first and third portions towards the region of saidsubstrate beneath said gate.
 69. The pixel imager system of claim 62,wherein the implant region includes a fourth portion, said fourthportion being lateral to the second portion in the direction of thegate.
 70. The pixel imager system of claim 69, where the implant dose ofthe fourth portion is between 2E11-1E13/cm².
 71. The pixel imager systemof claim 69, wherein the fourth portion extends further than the first,second, and third portions towards the region of said substrate beneathsaid gate.
 72. The pixel imager system of claim 71, wherein the first,second, and third portions of the implant region are formed by implantsangled between 0 and 5 degrees in the direction of the gate, said anglebeing measured away from a line normal to the surface of the substrate.73. The pixel imager system of claim 72, wherein the fourth portion isformed by an implant angled between 10 and 30 degrees in the directionof the gate, said angle being measured away from a line normal to thesurface of the substrate.
 74. The pixel imager system of claim 54,wherein at least one of said portion of implant regions are angled. 75.The pixel imager system of claim 54, wherein the pixel imager system isa CCD imager.
 76. The pixel imager system of claim 54, wherein the pixelimager system is a CMOS imager.
 77. The pixel imager system of claim 76,wherein said imager device is one of a three transistor (3T), fourtransistor (4T) five transistor (5T), six transistor (6T) or seventransistor (7T) architecture.